I also did not notice a decreased appetite for DRAM voltage. The 'Memory Holes' were not found in my samples. I advise you to not touch it at all, as 0.9 V is a wonderful number that allows you to train your memory at frequencies of 2133–4333 MHz. The safe limit for VDDG is up to and including 1.1 V. My recommendation is to use a manual VDDG with a value of 0.95 V (enough to overclock FCLK to 1800 MHz) or keep a 0.05 V gap between it and SoC.

By default, it is 0.950 V however, some motherboards may exceed the default level even with standard settings and may even cause a boot failure due to excessive voltage. The SoC voltage should be higher than requested by VDDG. Since CLDO_VDDG and CLDO_VDDP are regulated from the VDDCR_SoC plane, there is a rule for setting VDDG. The first is responsible for Infinity Fabric links between the two CCX on each CCD, and the second parameter is responsible for the long-range IFOP link between IO Die and CCD. In recent AGESA, CLDO_VDDG was split into two settings: VDDG CCD and VDDG IOD. It exists for the stabilization of high frequencies of FCLK. VDDG is the Infinity Fabric (IF) voltage, which, as you might have guessed, is responsible for the integrity of the data moving through IF.

CLDO as part of VDDG means that a dropout stabilizer is used for the voltage (LDO means 'low dropout level'). 'Zen 2' also introduced a new voltage setting called CLDO_VDDG.

Vddp voltage control